Field of the Invention
The field of the present application relates in general to a method of evaluating and controlling a semiconductor manufacturing process of a semiconductor chip having a plurality of microelectronic circuits on a semiconductor wafer and also to an apparatus for the evaluation of the semiconductor manufacturing process utilising the process flow of the semiconductor manufacturing process.
Brief Description of the Related Art
It will be appreciated that the term “semiconductor wafer” as used in this disclosure is intended to imply wafers used in the manufacture of all types of semiconductor devices, including, but not limited to, microelectronic circuits, such as memory devices, ASICS, logic circuits such as controllers or microprocessors, etc., liquid crystal panels, and photovoltaic devices.
The term “process flow” as used in in this disclosure means a series of process steps (and/or branching paths, which could also re-join each other or the series of process steps) in the semiconductor manufacturing process.
Current trends in the manufacturing of semiconductor devices by processing of the semiconductor wafers mean that overlay and critical dimension budgets shrink with shrinking ground rules and the semiconductor manufacturing processes are becoming more aggressive. Non-limiting examples of such aggressive semiconductor manufacturing processes include, but are not limited to, multiple patterning, and high aspect ratio etching or deposition of exotic materials on a surface of the semiconductor wafer. The non-uniformity of some of the semiconductor manufacturing processes over the semiconductor wafer surface and a plurality of semiconductor manufacturing process steps may result in non-uniform stress being applied to the semiconductor wafer.
One example of the issue that occurs is the so-called overlay error. This can occur when the semiconductor wafer deforms from one process step to a subsequent process step, e.g. from one lower layer to a subsequent layer on top of the lower layer, patterns in the upper layer become misaligned with respect to patterns in the lower layer. For the error free functioning of the semiconductor device, the relative position of the patterns on the different layers to each other is relevant. The reason for this misalignment can be multi-fold and may depend on the different process steps. It is therefore an aim of the method and apparatus described in this document to enable the evaluation and control of the semiconductor manufacturing process to identify and/or correct for such issues in the semiconductor manufacturing process. This evaluation and control is done by associating a plurality of data items with the process flow and then analysing the combination of the data items and the process flow.
A further issue that arises using the aggressive semiconductor manufacturing processes concerns the so-called critical dimensions (CDs). This term is used to indicate the geometrical dimensions of features of critical patterns on the surface of the semiconductor wafer. These features are measured after processing, such as the patterning of the lithographic layer, deposition or etching, etc., in order to verify the quality of the process steps, such as exposure and development process, by comparing the actual values to the target values and by determining the uniformity over the field, the semiconductor wafer and the lot.
In practice, there are multiple measurements, which need to be considered when deciding whether the semiconductor devices manufactured on the semiconductor wafer are likely to perform according to specifications. The use of the overlay measurements and CD measurements is merely used as an illustration.
The need to collect data documenting a semiconductor manufacturing process is known. For example, U.S. Pat. No. 8,396,583 (TSMC) teaches a method for fabricating a semiconductor device which includes collecting a plurality of manufacturing data sets. The manufacturing data sets are normalised and then used to predict the performance of one of the semiconductor manufacturing processes.
An older U.S. Pat. No. 5,866,437 (AMD) teaches a method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements based on comparisons of measurements of the critical dimensions with historic data.
U.S. Pat. No. 7,646,476 teaches a method of detecting process excursions based on the analysis of defect information of a semiconductor substrate.
None of these prior art publications teach the association of measurements of process step parameters with a process step, as part of the process flow, to enable the evaluation and control of the semiconductor manufacturing process.